Thin film transistor assembly, particularly suitable for liquid crystal display device, and process for fabricating the same

ABSTRACT

A method of fabricating a thin film transistor (TFT) assembly having a plurality of array lines, a plurality of pads, a plurality of link lines connecting the pads to the array lines, an insulating layer, and an electrode pattern formed on a substrate, and further having short-preventing structures for preventing electrical shorts between the pads and the link lines. The method includes the steps of forming the plurality of pads on the substrate, depositing the insulating layer on the substrate including over the pads, etching the insulating layer to form contact holes, and etching the insulating layer between the adjacent pads to expose a surface of the substrate to prevent a short between the adjacent pads from occurring, and forming the electrode pattern on the insulating layer by depositing and patterning an electrode layer such that the electrode pattern contacts the pads through the contact holes formed in the insulating layer. The steps of etching the insulating layer between the adjacent pads is performed concurrently with the etching step for forming the contact holes. In addition, the areas between adjacent pads are further etched concurrently with the step of etching the electrode layer.

CROSS REFERENCE TO RELATED ART

[0001] This application claims priority of Korean patent application No. 98-20196 filed on Jun. 1, 1998, the entire disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a thin film transistor (TFT) assembly, and in particular, to a TFT suitable for a liquid crystal display (LCD) device, and a method of fabricating the same.

[0004] 2. Description of the Related Art

[0005] Generally, a TFT is used as a switching element in, for example, an LCD device. A well known TFT assembly includes a substrate, gate and data lines formed on the substrate in a matrix pattern, and gate and data pads for transmitting drive signals from a drive circuit to the gate and data lines.

[0006]FIG. 1 schematically illustrates gate and data pads of a TFT assembly, and FIG. 2 shows an enlarged view of a circled portion C of FIG. 1 for illustrating a portion where gate pads and link lines are formed.

[0007] Referring first to FIG. 1, a TFT assembly comprises a plurality of gate pads 10 connected to gate lines (not shown) formed on a substrate 40, and a plurality of data pads 20 connected to data lines (not shown) formed on the substrate 40. The gate and data lines are generally arranged to form a matrix pattern (not shown). As shown in FIG. 2, gate drive signals are transmitted from a drive circuit (not shown) to the gate pads 10, and from the gate pads to the gate lines through link lines 11. The gate drive signals transmitted to the gate lines are further transmitted to corresponding thin film transistors to drive the same. Short circuits frequently occur during the manufacturing of the TFT assembly between adjacent pads 10 and between adjacent link lines 11 due to metal remainders or residues 14 a and 14 b, respectively.

[0008] The metal remainders 14 a and 14 b will be described in more detail with reference to FIGS. 3a and 3 b, which are sectional views taken along lines I-I and II-II of FIG. 2, respectively.

[0009] Referring first to FIG. 3a, there is provided a substrate 13 on which the gate pads 10 are deposited using, for example, an aluminum evaporation process. Formed on the gate pads 10 is a metal layer 16 made of, for example, molybdenum (Mo) to prevent hillock from occurring on the aluminum surfaces of gate pads 10. Deposited on the substrate 13 to cover the gate pads 10 and the metal layer 16 are, in order, a gate insulating layer 17 and a passivation layer 18 that are made of a silicon oxide or a silicon nitride. In addition, contact holes are formed by etching portions of the gate insulating and passivation layers 17 and 18, which correspond to the gate pads 10, using, for example, a masking process, such that the metal layer 16 is exposed. Indium tin oxide (ITO) electrodes 19 are formed on the passivation layer 18 such that they contact the metal layer 16 through the contact holes.

[0010] Referring to FIG. 3b, a structure of the link line portion is substantially the same as that of the pad portion shown in FIG. 3a except that there are no contact holes in the gate insulating and passivation layers 17 and 18. That is, portions of the gate insulating and passivation layers 17 and 18 corresponding to the link lines 11 are not etched. The ITO electrodes 19 are formed on the portions of the passivation layer 18 corresponding to the link lines 11.

[0011] In the above described TFT assembly, during an aluminum evaporation process for forming the pads 10 and the link lines 11, or during a masking process for forming the metal layer 16, metal remainders 14 a or 14 b may be formed on the substrate. The metal remainders 14 a or 14 b may electrically interconnect the adjacent pads 10 or the adjacent link lines 11, as shown in FIGS. 3a and 3 b. The metal remainders 14 a and 14 b cause a short circuit between the adjacent pads 10 and between the adjacent link lines 11.

[0012] In an effort to overcome this drawback, a short circuit inspecting device has been used to detect short circuits in the TFT assembly and to repair the same. For example, metal remainders (short circuits) may be disconnected using laser after being detected. However, this process is time consuming and reduces overall manufacturing productivity.

SUMMARY OF THE INVENTION

[0013] Accordingly, the present invention is directed to a TFT assembly and a method of fabricating the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.

[0014] It is an object of the present invention to provide a TFT assembly having a structure for preventing a short circuit from occurring between adjacent pads or between adjacent links.

[0015] It is another object of the present invention to provide a method of fabricating a TFT assembly including a step for preventing a short circuit from occurring between adjacent pads or between adjacent links.

[0016] Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0017] To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a method of fabricating a semiconductor device having a plurality of conductive structures formed on a substrate for transmitting signals, the method comprising the steps of forming a plurality of conductive structures on the substrate; depositing an insulating layer on the conductive structures and the substrate; and etching portions of the insulating layer between adjacent conductive structures to expose a surface of the substrate, thereby preventing an electrical short between the adjacent conductive structures.

[0018] According to another embodiment of the present invention, a method of fabricating a semiconductor device comprises the steps of forming a plurality of pads on the substrate; depositing an insulating layer on the substrate; and forming an electrode pattern on the insulating layer, the electrode pattern contacting the pads through a plurality of contact holes formed in the insulating layer, wherein the insulating layer between adjacent pads is etched to expose a surface of the substrate, whereby a short between the adjacent pads due to a metal remainder formed when the pads are formed is prevented.

[0019] According to another aspect of the present invention, a semiconductor device comprises a substrate; a plurality of conductive structures on the substrate; an insulating layer on the substrate and the conductive structures; an electrode pattern on the insulating layer, the electrode pattern contacting at least some of the conductive structures through a plurality of contact holes in the insulating layer; and at least one insulating channel between adjacent conductive structures, a surface of the substrate being exposed through the insulating channel.

[0020] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

[0022] In the drawings:

[0023]FIG. 1 schematically illustrates a conventional TFT assembly having data pads and gate pads;

[0024]FIG. 2 is an enlarged view of a circled portion C of FIG. 1 for illustrating short circuits occurring between pads and between link lines;

[0025]FIGS. 3a and 3 b are sectional views taken along lines I-I and II-II of FIG. 2, respectively;

[0026]FIGS. 4a to 4 c are sectional views taken along a line III-III of FIG. 6 and illustrate a pad portion of a TFT assembly as it undergoes sequential processing steps in accordance with a preferred embodiment of the present invention;

[0027]FIGS. 5a to 5 c are sectional views taken along a line IV-IV of FIG. 6 and illustrate a link line portion of a TFT assembly as it undergoes sequential processing steps in accordance with a preferred embodiment of the present invention; and

[0028]FIG. 6 schematically illustrates a TFT assembly according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0029] Reference will now be made in detail to the present preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. The same reference numbers are used in the drawings to refer to the same or like parts.

[0030]FIGS. 4a to 4 c show, in cross-section views, a portion of a TFT assembly where pads are formed as it undergoes sequential processing steps in accordance with a preferred embodiment of the present invention.

[0031] As shown in FIG. 4a, gate pads 111 are formed on a substrate 100 by, for example, an evaporation process, and a metal layer 121 is optionally formed on the gate pads 111 using, for example, a masking process. Preferably, the gate pads are made of aluminum or an aluminum alloy material, and the metal layer 121 is formed of molybdenum. Other suitable materials known in the art may also be used.

[0032] During the above steps, a metal remainder 113 may be formed, connecting the gate pads 111 to each other. This is caused by defective patterning of the metal layer 121 and/or the gate pads 111, and results in a short circuit between adjacent gate pads 111. However, even if the metal remainder 113 is formed, an insulating layer 131 and a passivation layer 133 are deposited on the substrate 100 to cover both the gate pads 111 and the metal layer 121.

[0033] Subsequently, as shown in FIG. 4b, portions of the insulating and passivation layers 131 and 133 corresponding to the gate pads 111 are dry-etched to form contact holes 132 for the ITO electrodes. Preferably at the same time, portions of the insulating and passivation layers 131 and 133 between the pads 111 are also dry-etched, so that a short circuit disconnecting channel or insulating channel 150 is formed while removing the metal remainder 113 connecting the adjacent gate pads 111, thereby disconnecting the short circuit.

[0034] Next, a conductive material such as an ITO material is deposited on the passivation layer 133 while contacting the metal layer 121 through the contacting holes 132, and is then wet-etched to form an ITO electrode pattern 141.

[0035] During the above steps, the metal remainder 113 may not be completely removed by dry-etching the insulating and passivation layers 131 and 133, particularly in the case where the metal remainder 113 is formed by a defective pattern of the gate pads, i.e., where the metal remainder 113 is an aluminum or aluminum alloy material. In the present invention, the metal remainder 113 is preferably further removed by the wet-etching step that is performed to form the ITO electrode pattern 141. The surface of the substrate which is exposed by etching the insulating layer is etched concurrently with the etching process for forming the electrode pattern. This ensures that short circuits between the pads will not occur.

[0036]FIGS. 5a to 5 c show, in cross-section views, a link line portion of the TFT assembly as it undergoes sequential processing steps in accordance with a preferred embodiment of the present invention.

[0037] Preferably, the insulating layer between adjacent link lines is etched simultaneously with the etching of the insulating layer between the adjacent pads. In other words, the steps shown in FIGS. 5a to 5 c are performed concurrently with the steps shown in FIGS. 4a to 4 c, respectively. That is, link lines 112 for transmitting signals from the gate pads 111 to the gate lines are formed concurrently with the gate pads 111 shown in FIG. 4a. Since insulating and passivation layers 131 and 133 are identical to those described with reference to FIGS. 4a to 4 c, the detailed description thereof is omitted.

[0038] However, since it is not necessary to form the ITO electrodes on the link lines 112, portions of the insulating and passivation layers 131 and 133 corresponding to the link lines 112 are not etched during the etching step shown in FIG. 4b. Therefore, only portions of the insulating and passivation layers 131 and 133 between adjacent link lines 112 are etched to form a short circuit disconnecting channel or insulating channel 150 while removing the metal remainder 113 a, thereby removing short circuits or electrical connections between the adjacent link lines.

[0039] An ITO electrode layer 143 is formed simultaneously with, and using the same steps as, the ITO electrode pattern 141 shown in FIG. 4c.

[0040] In the case where the metal remainder 113 a is not completely removed so that the short is not disconnected as shown in FIG. 5b, the metal remainder 113 a is completely removed by the wet-etching process that is performed when ITO is etched to form the electrode pattern 143.

[0041] Therefore, as shown in FIG. 6, the short-disconnecting channel 150 is formed running along between the adjacent pads 111 and between the adjacent link lines 112. Preferably, the short-disconnecting channel 150 is formed extending toward the link lines by etching the insulating layer between the adjacent link lines. The short-disconnecting channel may optionally be filled with an insulating material.

[0042] While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments and various modifications are possible. For example, the concept of the present invention may be used in making a plasma display panel as well as a TFT LCD. Thus, it is intended that the present invention cover the modifications and variations of the embodiments that come within the scope of the appended claims and their equivalents. 

What is claimed is:
 1. A method of fabricating a semiconductor device having a plurality of conductive structures formed on a substrate for transmitting signals, the method comprising the steps of: (a) forming a plurality of conductive structures on the substrate; (b) depositing an insulating layer on the conductive structures and the substrate; and (c) etching portions of the insulating layer between adjacent conductive structures to expose a surface of the substrate, thereby preventing an electrical short between the adjacent conductive structures.
 2. The method of claim 1, wherein the insulating layer comprises a first insulating layer and a passivation layer.
 3. The method of claim 1, wherein the portions of the insulating layer between adjacent conductive structures are dry-etched.
 4. The method of claim 1, wherein the semiconductor device is a thin film transistor device for a liquid crystal display.
 5. The method of claim 1, wherein the semiconductor device is a thin film transistor assembly having array lines, and wherein the conductive structures include pads for transmitting signals to the array lines.
 6. The method of claim 5, further comprising the step of forming a metal layer on the pads.
 7. The method of claim 6, wherein the pads include aluminum or an aluminum alloy and the metal layer on the pads includes molybdenum.
 8. The method of claim 1, wherein the semiconductor device is a thin film transistor assembly having array lines and pads, and wherein the conductive structures are link lines for transmitting signals from the pads to the array lines.
 9. The method of claim 1, wherein the semiconductor device is a thin film transistor assembly having array lines, and wherein the conductive structures include pads and link lines for transmitting signals to the array lines.
 10. The method of claim 9, wherein the insulating layer between adjacent link lines and the insulating layer between adjacent pads are etched concurrently.
 11. The method of claim 1, further comprising the steps of: (d) etching portions of the insulating layer over the conductive structure to form a plurality of contact holes for electrodes, wherein step (d) is performed concurrently with step (c).
 12. The method of claim 11, further comprising the steps of: (e) forming a conductive layer on the substrate including the contact holes and areas between the conductive structures; and (f) etching portions of the conductive layer to form an electrode pattern which contacts the conductive structures through the contact holes, wherein the etched portions include the areas between adjacent conductive structures to expose a surface of the substrate, thereby preventing an electrical short between adjacent conductive structures.
 13. The method of claim 12, wherein the portions of the conductive layer are wet-etched.
 14. The method of claim 12, wherein the conductive layer is formed of indium tin oxide.
 15. A method of fabricating a semiconductor device comprising the steps of: (a) forming a plurality of pads on the substrate; (b) depositing an insulating layer on the substrate; and (c) forming an electrode pattern on the insulating layer, the electrode pattern contacting the pads through a plurality of contact holes formed in the insulating layer, wherein the insulating layer between adjacent pads is etched to expose a surface of the substrate, whereby a short between the adjacent pads due to a metal remainder formed when the pads are formed is prevented.
 16. The method of claim 15, wherein the semiconductor device is a thin film transistor device for a liquid crystal display.
 17. The method of claim 15, wherein the insulating layer comprises a first insulating layer and a passivation layer.
 18. The method of claim 15, wherein the electrode pattern includes indium tin oxide.
 19. The method of claim 15, wherein the insulating layer between adjacent pads is dry-etched.
 20. The method of claim 15, wherein the etching of the insulating layer between the adjacent pads is performed concurrently with the step of forming the electrode pattern.
 21. The method of claim 15, wherein the contact holes are formed by etching portions of the insulating layer corresponding to the pads, and wherein the etching of the insulating layer between the adjacent pads is performed concurrently with the step of etching the portions of the insulating layer corresponding to the pads.
 22. The method of claim 15, further comprising the step of forming a metal layer on the pads.
 23. The method of claim 22, wherein the pads include aluminum or an aluminum alloy and the metal layer on the pads includes molybdenum.
 24. A semiconductor device comprising: a substrate; a plurality of conductive structures on the substrate; an insulating layer on the substrate and the conductive structures; an electrode pattern on the insulating layer, the electrode pattern contacting at least some of the conductive structures through a plurality of contact holes in the insulating layer; and at least one insulating channel between adjacent conductive structures, a surface of the substrate being exposed through the insulating channel.
 25. The device of claim 24, wherein the insulating layer comprise a first insulating layer and a passivation layer.
 26. The device of claim 24, wherein the electrode pattern is formed of indium tin oxide.
 27. The device of claim 24, wherein the insulating channel is formed by etching the insulating layer between the adjacent conductive structures.
 28. The device of claim 24, wherein the insulating channel is formed by dry-etching the insulating layer between the adjacent conductive structures.
 29. The device of claim 24, wherein the semiconductor device is a thin film transistor device used to control a liquid crystal display.
 30. The semiconductor device of claim 24, wherein the semiconductor device is a thin film transistor assembly having array lines, and wherein the conductive structures are pads for transmitting signals to the array lines.
 31. The semiconductor device of claim 30, further comprising a metal layer on the pads.
 32. The semiconductor device of claim 31, wherein the pads are formed of aluminum or an aluminum alloy and the metal layer on the pads is formed of molybdenum.
 33. The semiconductor device of claim 24, wherein the semiconductor device is a thin film transistor assembly having array lines and pads, and wherein the conductive structures are link lines for transmitting signals from the pads to the array lines.
 34. The semiconductor device of claim 24, wherein the semiconductor device is a thin film transistor assembly having array lines, and wherein the conductive structures include pads and link lines for transmitting drive signals to the array lines. 